Active speaker in the VLSI and semiconductor community — workshops, tech talks, and IEEE sessions on RTL design, SoC integration, and AI chip development.
A full-day hands-on workshop that goes beyond RTL. Work through real hardware architecture problems, participate in whiteboard deep-dives and group discussions, and learn practical thinking routines used by top hardware engineers. Hosted by the IEEE CEDA Bangalore Chapter in collaboration with Sai Vidya Institute of Technology.
Co-speaker: Milind Parelkar — Principal Engineer, Qualcomm US · Founder, fpgadesign.io · Author of Demystifying Digital Design Interview
Register Now →Another IEEE talk is in the works. Details will be announced here once confirmed.
I am an active speaker in IEEE events focused on VLSI, semiconductor design, and engineering education. My sessions focus on the gap between academic learning and real-world design practice — specifically how engineers think through trade-offs, not just how they write code.
Topics I speak on:
A technical talk bridging the gap between academic ASIC design learning and real-world semiconductor industry practice — covering industry workflows, design challenges, verification processes, and career paths in VLSI. Delivered to students at Dayananda Sagar College of Engineering, Bengaluru.
View on IEEE vTools →Open to IEEE sessions, university workshops, and industry panels on VLSI, RTL design, and AI chip development.
Connect on LinkedIn →