Active speaker in the VLSI and semiconductor community — workshops, tech talks, and IEEE sessions on RTL design, SoC integration, and AI chip development.
A hands-on workshop on RTL design thinking — covering design decisions under real constraints, debugging strategies, and how designs behave beyond simulation. Targeted at students and early engineers in the VLSI space.
Invited talk at the 6th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications. The conference brings together researchers and engineers from academia and industry across embedded systems, SoC design, AI/ML accelerators, and advanced packaging.
View Conference →I am an active speaker in IEEE events focused on VLSI, semiconductor design, and engineering education. My sessions focus on the gap between academic learning and real-world design practice — specifically how engineers think through trade-offs, not just how they write code.
Topics I speak on:
Open to IEEE sessions, university workshops, and industry panels on VLSI, RTL design, and AI chip development.
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