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Staff Engineer at ARM

Helping ASIC engineers
break into product companies.

9 years building AI chips at ARM, Qualcomm, and Granite River Labs — including camera ISP for Meta Ray-Ban XR. Now helping engineers make the same move: from service companies to product-based roles.

9+Years in RTL
5+Tape-outs
88+Mentorship sessions
5.0★ Mentor rating
Palash Khandale — RTL Design & SoC Integration Engineer

Where this comes from

I work on product-level RTL and SoC integration — not academic projects. My work has involved real constraints: synthesis timelines, silicon behaviour, cross-team integration, and debugging issues that only show up in the full system context.

My focus has been understanding how designs behave under real conditions, not just in simulation. That means thinking in terms of timing budgets, clock domains, power intent, and integration boundaries — before writing a single line of code.

I work at the intersection of design and integration — where the real problems live.
Full background →
Palash Khandale at DSCE IEEE talk Palash Khandale speaking at podium Palash Khandale presenting ASIC design talk

Engineers who made the jump

"Cleared ARM's RTL round after our sessions. The prep was exactly what the interviewers tested."
★★★★★  ·  Now at ARM
"Palash's mock interviews were tougher than Samsung Semiconductor's actual rounds. Walked in confident."
★★★★★  ·  Now at Samsung Semiconductor
"Targeted Altera specifically. The RTL depth Palash helped me build was the difference — got the offer."
★★★★★  ·  Now at Altera
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